Principal Engineer - Analog and Mixed-Signal Physical Design

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and is responsible for powering Microsoft’s Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft’s online businesses, including Azure, Microsoft 365, Teams, OneDrive, Xbox, and other global services.

As Microsoft’s cloud and silicon investments continue to grow, the ability to deliver advanced analog and mixed-signal silicon IP on schedule, at high quality, and with strong execution discipline is critical. We are looking for a Principal Engineer – Analog and Mixed-Signal Physical Design to serve as a hands-on technical contributor who can drive physical implementation, timing closure, physical design verification, and custom IP integration for analog and mixed-signal designs.

This is a hands-on Principal role, not a planning-only or coordination-only position. The ideal candidate brings deep Fusion Compiler-based physical implementation expertise, strong timing closure and physical verification experience, and sufficient custom layout understanding to partner effectively with analog design and layout teams while directly executing critical implementation and debug work.

#SCHIE

• Owner of 1st party analog assembly for critical Die-to-Die and custom interface IP assembly, driving hands-on physical design implementation for analog and mixed-signal IP blocks, including floorplanning, placement, routing, optimization, ECO implementation, and closure debug.
• Execute and guide Fusion Compiler-based APR flows, with direct ownership of implementation quality, timing convergence, physical design verification readiness, and signoff closure.
• Serve as the technical bridge between analog design, custom layout, physical design, timing, physical verification, CAD/methodology, and silicon integration teams.
• Perform timing analysis and closure activities across analog and mixed-signal-adjacent IP, including constraint review, timing debug, implementation tradeoffs, and signoff readiness.
• Partner with custom layout engineers to ensure layout feasibility, integration quality, physical verification closure, and timing/implementation convergence without positioning this role as a pure custom layout owner.
• Lead internal and external/V-team execution through hands-on technical direction, deliverable review, quality expectations, and schedule alignment.
• Debug and resolve complex implementation issues related to physical design, timing closure, extraction, physical verification, layout integration, reliability, and release readiness.
• Coordinate implementation activities across architecture, circuit design, layout, CAD/methodology, verification, product engineering, and silicon integration stakeholders.
• Contribute to design reviews, implementation quality improvements, signoff planning, and broader execution strategy for analog, mixed-signal, and custom IP physical design deliverables.
• Mentor engineers and provide Principal-level technical leadership while remaining directly engaged as a doer in critical implementation and closure work 

Required Qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Ability to meet Microsoft, customer, and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check. This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.  

Preferred

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field AND 10+ years of technical engineering experience in silicon development, physical design, timing closure, or related disciplines.
• Experience with analog and mixed-signal IP physical implementation, custom IP integration, or mixed-signal-adjacent implementation flows.
• Knowledge of PrimeTime timing analysis, constraint debug, timing ECO strategy, and timing closure methodologies.
• Working understanding of custom analog layout, Virtuoso-based layout methodologies, physical verification, extraction, and layout integration considerations.
• Familiarity with advanced-node implementation challenges and cross-functional integration across architecture, circuit design, layout, CAD/methodology, product engineering, and silicon integration teams.
• Strong debugging, analytical, problem-solving, communication, and cross-functional collaboration skills.
• Proven Principal-level technical leadership across large-scale, cross-functional engineering efforts while remaining hands-on in execution.
• Experience with Fusion Compiler-based APR and physical implementation flows, including floorplanning, placement, clock tree synthesis, routing, optimization, ECO implementation, and closure debug.
• Experience with physical design verification, implementation signoff, and silicon quality methodologies.
• Experience performing hands-on physical implementation and timing closure for complex silicon IP from concept through tapeout or equivalent silicon development milestones.
• Experience leading or coordinating distributed engineering teams, including vendor or external/V-team resources, while remaining directly involved in technical execution.

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.