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Microloft

Senior Emulation Engineer

Posted 16 Hours Ago
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In-Office
Mountain View, CA, USA
120K-261K Annually
Senior level
In-Office
Mountain View, CA, USA
120K-261K Annually
Senior level
Develop and optimize scalable SoC emulation models and verification environments for Microsoft AI accelerators. Create verification plans, reusable monitors, trackers, debug flows, assertions, and coverage models. Triage failures across simulation and emulation, automate verification workflows with Makefiles and scripts, and support functional, performance, and power verification. Collaborate with architecture, design, firmware, validation, and product engineering teams across sites.
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Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior Emulation Engineer to help achieve that mission. 
 

The AI Silicon Engineering (AISiE) SoC Design Verification team verifies Microsoft’s latest AI accelerators, working hand in hand with systems, firmware, architecture, design, validation, and product engineering teams. We are seeking a Senior Emulation Engineer who can partner across these disciplines to develop the verification environments and test cases that bring these accelerators to production with high quality. 

As a Senior Emulation Engineer on the AISiE SoC Design Verification team, develop complex, scalable verification environments optimized for emulation platforms to support functional, performance, and power verification at the SoC level. Enable software and firmware teams to leverage emulation models for shift-left verification and improve post-silicon readiness. With design growing exponentially and schedules shrinking in, hardware assisted verification technologies like emulation will be critical for design verification milestones. 



Responsibilities
  • Build, validate and automate emulation models with constant improvement in runtime efficiency. Preferred platforms include Zebu and Palladium.   
  • Collaborate with architects and design engineers to define verification plans, including strategy, test environments, and requirements for IP/Subsystem/SoC-level verification.  
  • Develop reusable verification components, including monitors, trackers, debug flows, assertions, and functional coverage models.  
  • Triage and debug failures across testbenches, simulation, and emulation environments.  
  • Develop Makefiles and automation scripts to enable scalable and efficient verification flows.  
  • Apply Agile methodologies, including participation in code reviews, sprint planning, and continuous integration practices.  
  • Collaborate effectively with cross-functional teams across multiple sites and geographies 

Qualifications

Required Qualifications:

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Other Requirements:

  • Ability to meet Microsoft, customer, and/or government security screening requirements is required for this role. These requirements include, but are not limited to, the following specialized security screening: Microsoft Cloud Background Check. This position is required to pass the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 

Preferred Qualifications: 

  • Doctorate in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience OR equivalent experience.
  • AI Accelerator, CPU, graphics, or NPU design verification at SoC.
  • Emulation platform and its associated technologies including transactors, speed adapters, virtual solutions.
  • Experience on IO subsystem including PCIe, Ethernet, SPI interfaces.
  • Possessing full stack knowledge across Si lifecycle with collaboration across RTL, firmware, DV, platform teams.

#SCHIE #AISIE 

 
 
 


Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay


This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.



Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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