Jobs at MicrofluidX

Design and verify digital circuits for memory products (especially NAND). Develop RTL, firmware, and gate-level netlists; run post-layout simulation, netlist bring-up, and silicon validation. Define architecture and verification plans, collaborate with cross-functional teams, and apply AI tools to aid design and verification.

Customer-facing technical leader who engages early with strategic customers to design end-to-end memory and storage solutions for AI, cloud, and data-center platforms. Drives architecture decisions, secures design wins, aligns technical strategy with sales, and enables cross-functional handoff to engineering and deployment teams.

Own and grow a strategic global hyperscale customer relationship by executing account strategy, driving revenue and margin, managing multi-product pipelines, and coordinating cross-functional teams to align Micron solutions with customer needs.

Develop and deploy machine learning and generative AI solutions for early PDN/power-integrity modeling. Predict IR drop, voltage droop, current density, and electromigration risk; enable AI-assisted power-grid, bump, package-PDN, and decap optimization; automate root-cause analysis and design-space exploration using historical design, simulation, and silicon data. Collaborate with design, CAD, package, and product teams and deliver production-quality software to scale AI-enabled PDN workflows.

Lead and support global performance management programs through project leadership, needs analysis, solution design, implementation, training delivery, stakeholder coordination, and program evaluation. Develop and maintain program content, curate learning paths, perform skills and gap analyses, and forecast development needs to align with business strategy.

Lead SoC functional verification for an ASIC controller: define verification architecture/strategy, develop module-to-SoC test plans, coordinate multi-team verification, apply UVM and emulation, and leverage Gen-AI to improve verification efficiency and tape-out success.

Lead embedding of AI and automation into memory circuit design workflows to improve floorplanning, placement, routing, simulation, and tape-out iteration reduction using historical design and silicon data, collaborating across design, CAD, and manufacturing teams.

Design and verify electronics and PCBs for semiconductor SSD test equipment. Develop digital (FPGA, PCIe, DDR) and analog/power subsystems, perform signal/power integrity simulations (HyperLynx), prototype and debug with lab instruments, ensure DFM/DFT compliance, manage revisions, support qualification and production issues, and run DOE and reporting related to PCIe-based SSD testing.

Design, architect, validate and transition mechanical and thermal subsystems for advanced electronic memory systems. Lead system bring-up, thermal/structural characterization, debugging, test plan development, and production transfer while coordinating across hardware, firmware, software and manufacturing teams to ensure reliability and quality.

Design and implement digital ASIC logic across the full chip lifecycle: specifications, microarchitecture, RTL (SystemVerilog), simulation, synthesis, timing closure, linting, CDC, and top-level integration. Leverage GenAI and agentic tools to improve productivity and collaborate with cross-functional teams on interfaces like PCIe, NVMe, DRAM, NAND, and AXI.

Lead RTL micro‑architecture, implementation, and debug for complex ASIC subsystems. Drive front‑end design flow (lint, CDC, synthesis, ECO), integrate IP, collaborate with verification/STA/physical teams, build automation scripts, and apply AI‑assisted tools to improve productivity and silicon quality from concept to production.

Design and verify NAND Flash analog and digital circuits: decompose system functions, perform transistor-level design and post-layout simulation, validate via block/chip simulations, collaborate cross-functionally on performance, power, manufacturability, reliability, and use AI-assisted tools for debug and data analysis.

Lead Micron Ventures as corporate VC head: define investment strategy, source and diligence deals, structure and recommend investments, partner with business and technical leaders to create strategic value, build and lead the investment team, and act as external ambassador and internal advisor on technology and M&A trends.

Lead architecture and platform-level electrical design for SSD tester systems, covering host compute, PCIe/topology, high-speed interconnects, DUT interfaces, power delivery, and integration. Drive designs from concept through BOM, schematic, SI/PI-aware PCB implementation, lab bring-up, verification, and manufacturability. Collaborate across electrical, mechanical, software, and manufacturing teams, mentor engineers, and partner with customers to define requirements and roadmaps while modernizing systems for performance and reliability.

Lead analog/mixed-signal NAND circuit design and verification, architecting algorithms, waveforms, and floorplans. Drive simulation, optimization, parasitic extraction, and layout guidance. Develop AI/LLM-assisted design flows and verification automation. Collaborate cross-functionally to ensure manufacturability, reliability, cost, and time-to-market while mentoring engineers and producing documentation.

Lead layout-driven architecture exploration for next-generation memory modules and form factors. Perform feasibility studies, define routing/topology/via strategies, co-optimize with SI/PI teams, establish layout methodologies and design rules for >10–20+ Gb/s signaling, drive adoption of advanced PCB technologies, influence standards, and mentor junior engineers.

Lead NAND array circuit design: develop array waveforms, plan wordline/bitline architecture, perform die-size and power analysis, create X/Y/array schematics, run SPICE simulations, guide layout and parasitic extraction, build Python automation and AI-assisted EDA utilities, collaborate with firmware/analog/validation and cross-functional teams, and maintain documentation to optimize cost, quality, reliability, and time-to-market.

Lead analysis of DDR and emerging memory technologies across electrical, thermal, power, and performance domains. Identify performance gaps, evaluate cost/latency/bandwidth tradeoffs, provide actionable design guidance, align cross-functional teams, and deliver technical recommendations. Use AI tools to build models, summarize data, and mentor others as part of a technical leadership career path.

Design and prototype LLM-powered agents and agentic workflows for engineering and manufacturing use cases. Build agents with planning, tool-use, memory, and reflection; integrate with APIs, databases, and EDA environments; perform model and prompt evaluation; and collaborate with cross-functional engineering and data science teams to deliver prototypes.

Lead automotive TAM and market modeling. Conduct market, technology, ecosystem, and competitive analysis to inform automotive strategic and GTM plans. Collaborate with product, architecture, business development, and strategic planning teams to build business cases, create marketing collateral, and support sales enablement. Represent Micron at trade shows; up to 10% travel.